System-on-chip (SoC) technology presents a major revolution in the design of integrated circuits because of the unprecedented levels of integration possible. A system-on-chip has both hardware and software components. The hardware components can include one or more central processing units (CPUs), memory systems, special functions devices, buses, and interfaces; whereas, operating systems, applications, and drivers are exemplary software components.
Because the hardware components execute the software components, these hardware and software components are dependant on each other. Despite this, the hardware and software components typically are separately developed, often by different people. Since silicon turns (each “silicon turn” is a complete fabrication of chip) can account for a large portion of the total cost and time for developing a system-on-chip, considerable hardware verification is performed prior to fabrication. One important technique for performing functional verification of a system-on-chip involves executing the software components with real data to test a preselected percentage of the system-on-chip's total state space, a set of all reachable system states and transitions among these states.
Numerous methods have been used to perform co-verification of hardware and software components. For example, one technique involves modeling one or more hardware components in a Hardware Description Language (HDL) such as Verilog and simulating the modeled components by running the software components on an event-driven gate-level logic simulator. With current designs, presently available simulators and workstations have proven unsatisfactory because performance of such models ranges between approximately one and one thousand cycles per second, which is inadequate for operating the software components.
Similarly, one or more hardware components can be modeled at the instruction level in a high-level programming language, such as C or C++, by an instruction set simulator (ISS). The instruction set simulator can be readily developed and can operate the software components and modeled hardware components at a clock frequency of about ten thousand to one hundred thousand cycles per second. This is an improvement over the event driven simulators discussed above, but instruction-level instruction set simulators also have substantial limitations. Instruction set simulators, for instance, are not useful when cycle level accuracy is needed to model software execution speed, which often is necessary in media processing systems and other real-time embedded systems. A fully accurate cycle level instruction set simulator, which employs accurate models of internal pipelines, speculative execution, and cache and memory management unit (MMU) behavior, is very difficult to design. Further, since the central processing unit's cache and/or memory management unit typically are not modeled, instruction set simulators do not present the same sequence of transactions to both the modeled hardware components and physical hardware components.
Custom prototypes of new hardware components can be produced with one or more field programmable gate arrays (FPGAs) and/or with hardware assisted accelerators or emulators, such as the Palladium Accelerator/Emulator provided by Cadence Design Systems, Inc., of San Jose, Calif. The use of field programmable gate arrays however is limited to small, modular hardware components, while hardware assisted accelerators require custom processors, which can be expensive.
Physical platform development prototype boards, such as an ARM Integrator Development Board platform produced by ARM Limited in Cambridge, England, provide a platform with central processing units, memory systems, and other devices that are interconnected by buses and that are suitable for developing new hardware and software components for a system-on-chip designs. Each new component typically is independently debugged, generally requiring specially-developed testbench programs. Once produced in synthesizable register transfer level (RTL) form, the new components can be synthesized into a field programmable gate array in a field programmable gate array for verification at full speed. However, the new components, once in synthesizable register transfer level form, are difficult to debug and revise, resulting in increased cost and longer development times.
In view of the foregoing, a need exists for an improved design verification system that overcomes the aforementioned obstacles and deficiencies of currently-available design verification systems.